During the development of the integrated circuit (IC) fabrication technology, photolithography process has always been a major process for fabricating semiconductor patterns. For a photolithography process, various patterns on a photolithographic mask are sequentially projected on a substrate coated with a photoresist layer with a precise alignment by an exposure apparatus. After a developing process, the designed patterns are formed on the substrate.
With the continuous shrinkage of the critical dimension (CD) of the semiconductor technology, the cost of the optical exposure apparatus and the high resolution mask has become a major limitation for the development of the semiconductor technology. Currently, the cost of the exposure process and related cost of the semiconductor manufacture is in a range of approximately 35%˜40% of the total cost of the semiconductor manufacturing. When the substrate with diameter of 450 mm is introduced, the cost of the exposure apparatus may be increased in a range of approximately 50%˜60% of the total cost of the semiconductor manufacture.
Some processes have been developed to substitute the photolithography process, such as the multiple e-beam lithography technology, or the nano-imprinting technology, etc. However, the multiple e-beam lithography technology is more expensive; and its throughput is slow due to limited electron current that can be used with electron guns. The nano-imprinting technology is limited by the high defect density (˜50-100 times more than the photolithography method).
Therefore, a low-cost patterning apparatus and patterning method is of demand. The disclosed apparatus and method are directed to solve one or more problems set forth above and other problems.